PCI Express* Registers (D1:F0)
6.1.14
SSTS1—Secondary Status
B/D/F/Type:
Address Offset:
Default Value:
Access:
0/1/0/PCI
1E–1Fh
0000h
RWC, RO
16 bits
Size:
SSTS1 is a 16-bit status register that reports the occurrence of error conditions
associated with secondary side (i.e., PCI Express side) of the "virtual" PCI-PCI bridge
embedded within GMCH.
Bit
Access &
Default
Description
15
RWC
0b
Detected Parity Error (DPE): This bit is set by the Secondary Side
for a Type 1 Configuration Space header device whenever it receives
a Poisoned TLP, regardless of the state of the Parity Error Response
Enable bit in the Bridge Control Register.
14
13
RWC
0b
Received System Error (RSE): This bit is set when the Secondary
Side for a Type 1 configuration space header device receives an
ERR_FATAL or ERR_NONFATAL.
RWC
0b
Received Master Abort (RMA): This bit is set when the Secondary
Side for Type 1 Configuration Space Header Device (for requests
initiated by the Type 1 Header Device itself) receives a Completion
with Unsupported Request Completion Status.
12
11
RWC
0b
Received Target Abort (RTA): This bit is set when the Secondary
Side for Type 1 Configuration Space Header Device (for requests
initiated by the Type 1 Header Device itself) receives a Completion
with Completer Abort Completion Status.
RO
0b
Signaled Target Abort (STA): Not Applicable or Implemented.
Hardwired to 0. The GMCH does not generate Target Aborts (the
GMCH will never complete a request using the Completer Abort
Completion status).
10:9
8
RO
00b
DEVSEL# Timing (DEVT): Not Applicable or Implemented.
Hardwired to 0.
RWC
0b
Master Data Parity Error (SMDPE): When set, this bit indicates
that the GMCH received across the link (upstream) a Read Data
Completion Poisoned TLP (EP=1). This bit can only be set when the
Parity Error Enable bit in the Bridge Control register is set.
7
6
RO
0b
Fast Back-to-Back (FB2B): Not Applicable or Implemented.
Hardwired to 0.
RO
0b
Reserved
5
RO
0b
66/60 MHz capability (CAP66): Not Applicable or Implemented.
Hardwired to 0.
4:0
RO
Reserved
00h
Datasheet
173
INTEL [ INTEL ]
