PCI Express* Registers (D1:F0)
Bit
4
Access &
Description
Default
RO
1b
Capabilities List (CAPL): Indicates that a capabilities list is
present. Hardwired to 1.
3
RO
0b
INTA Status (INTAS): Indicates that an interrupt message is
pending internally to the device. Only PME and Hot Plug sources feed
into this status bit (not PCI INTA-INTD assert and de-assert
messages). The INTA Assertion Disable bit, PCICMD1[10], has no
effect on this bit.
2:0
RO
Reserved
000b
6.1.5
RID1—Revision Identification
B/D/F/Type:
Address Offset:
Default Value:
Access:
0/1/0/PCI
08h
00h
RO
8 bits
Size:
This register contains the revision number of the GMCH device 1. These bits are read
only and writes to this register have no effect.
Bit
Access &
Default
Description
7:0
RO
00h
Revision Identification Number (RID1): This is an 8-bit value that
indicates the revision identification number for the GMCH Device 1.
Refer to the Intel® G35 Express Chipset Specification Update for the
value of the Revision ID register.
6.1.6
CC1—Class Code
B/D/F/Type:
Address Offset:
Default Value:
Access:
0/1/0/PCI
09–0Bh
060400h
RO
Size:
24 bits
This register identifies the basic function of the device, a more specific sub-class, and
a register- specific programming interface.
Bit
23:16
15:8
7:0
Access &
Default
Description
RO
06h
Base Class Code (BCC): This field indicates the base class code for
this device. This code has the value 06h, indicating a Bridge device.
RO
04h
Sub-Class Code (SUBCC): This field indicates the sub-class code for
this device. The code is 04h indicating a PCI to PCI Bridge.
RO
00h
Programming Interface (PI): This field indicates the programming
interface of this device. This value does not specify a particular
register set layout and provides no practical use for this device.
Datasheet
169
INTEL [ INTEL ]
