PCI Express* Registers (D1:F0)
6.1.10
SBUSN1—Secondary Bus Number
B/D/F/Type:
Address Offset:
Default Value:
Access:
0/1/0/PCI
19h
00h
RW
8 bits
Size:
This register identifies the bus number assigned to the second bus side of the "virtual"
bridge (i.e., to PCI Express-G). This number is programmed by the PCI configuration
software to allow mapping of configuration cycles to PCI Express-G.
Bit
Access &
Default
Description
7:0
RW
Secondary Bus Number (BUSN): This field is programmed by
00h
configuration software with the bus number assigned to PCI Express.
6.1.11
SUBUSN1—Subordinate Bus Number
B/D/F/Type:
Address Offset:
Default Value:
Access:
0/1/0/PCI
1Ah
00h
RW
8 bits
Size:
This register identifies the subordinate bus (if any) that resides at the level below PCI
Express-G. This number is programmed by the PCI configuration software to allow
mapping of configuration cycles to PCI Express-G.
Bit
Access &
Default
Description
7:0
RW
00h
Subordinate Bus Number (BUSN): This register is programmed by
configuration software with the number of the highest subordinate bus
that lies behind the Device 1 bridge. When only a single PCI device
resides on the PCI Express segment, this register will contain the
same value as the SBUSN1 register.
Datasheet
171
INTEL [ INTEL ]
