PCI Express* Registers (D1:F0)
Bit
3
Access &
Default
Description
RO
0b
Special Cycle Enable (SCE): Not Applicable or Implemented.
Hardwired to 0.
2
RW
0b
Bus Master Enable (BME): This bit controls the ability of the PEG
port to forward Memory and IO Read/Write Requests in the upstream
direction. This bit does not affect forwarding of Completions from the
primary interface to the secondary interface.
0 = This device is prevented from making memory or IO requests to its
primary bus. Note that according to PCI Specification, as MSI
interrupt messages are in-band memory writes, disabling the bus
master enable bit prevents this device from generating MSI
interrupt messages or passing them from its secondary bus to its
primary bus. Upstream memory writes/reads, I/O writes/reads,
peer writes/reads, and MSIs will all be treated as invalid cycles.
Writes are forwarded to memory address 000C_0000h with byte
enables de-asserted. Reads will be forwarded to memory address
000C_0000h and will return Unsupported Request status (or
Master abort) in its completion packet.
1 = This device is allowed to issue requests to its primary bus.
Completions for previously issued memory read requests on the
primary bus will be issued when the data is available.
1
0
RW
0b
Memory Access Enable (MAE):
0 = All of device 1's memory space is disabled.
1 = Enable the Memory and Pre-fetchable memory address ranges
defined in the MBASE1, MLIMIT1, PMBASE1, and PMLIMIT1
registers.
RW
0b
IO Access Enable (IOAE):
0 = All of device 1's I/O space is disabled.
1 = Enable the I/O address range defined in the IOBASE1, and
IOLIMIT1 registers.
Datasheet
167
INTEL [ INTEL ]
