PCI Express* Registers (D1:F0)
6.1.4
PCISTS1—PCI Status
B/D/F/Type:
Address Offset:
Default Value:
Access:
0/1/0/PCI
06–07h
0010h
RO, RWC
16 bits
Size:
This register reports the occurrence of error conditions associated with primary side of
the "virtual" Host-PCI Express bridge embedded within the GMCH.
Bit
Access &
Default
Description
15
RO
0b
Detected Parity Error (DPE): Not Applicable or Implemented.
Hardwired to 0. Parity (generating poisoned TLPs) is not supported
on the primary side of this device (error forwarding is not
performed).
14
RWC
0b
Signaled System Error (SSE): This bit is set when this Device
sends an SERR due to detecting an ERR_FATAL or ERR_NONFATAL
condition and the SERR Enable bit in the Command register is 1.
Both received (if enabled by BCTRL1[1]) and internally detected
error messages affect this field.
13
12
RO
0b
Received Master Abort Status (RMAS): Not Applicable or
Implemented. Hardwired to 0. The concept of a master abort does
not exist on primary side of this device.
RO
0b
Received Target Abort Status (RTAS): Not Applicable or
Implemented. Hardwired to 0. The concept of a target abort does
not exist on primary side of this device.
11
RO
0b
Signaled Target Abort Status (STAS): Not Applicable or
Implemented. Hardwired to 0. The concept of a target abort does
not exist on primary side of this device.
10:9
8
RO
DEVSELB Timing (DEVT): This device is not the subtractively
decoded device on bus 0. This bit field is therefore hardwired to 00
to indicate that the device uses the fastest possible decode.
RO
0b
Master Data Parity Error (PMDPE): Because the primary side of
the PEG's virtual PCI-to-PCI bridge is integrated with the GMCH
functionality there is no scenario where this bit will get set. Because
hardware will never set this bit, it is impossible for software to have
an opportunity to clear this bit or otherwise test that it is
implemented. The PCI specification defines it as a RWC, but for this
implementation an RO definition behaves the same way and will
meet all Microsoft testing requirements.
This bit can only be set when the Parity Error Enable bit in the PCI
Command register is set.
7
6
5
RO
0b
Fast Back-to-Back (FB2B): Not Applicable or Implemented.
Hardwired to 0.
RO
0b
Reserved
RO
0b
66/60MHz capability (CAP66): Not Applicable or Implemented.
Hardwired to 0.
168
Datasheet
INTEL [ INTEL ]
