DRAM Controller Registers (D0:F0)
Therefore, after the global interrupt is cleared by software, software must look at the
instantaneous status in the TSS register.
All bits in this register are reset to their defaults by PLTRST#.
Bit
15:10
9
Access &
Default
Description
RO
00h
Reserved
RWC
0b
Was Catastrophic Thermal Sensor Interrupt Event (WCTSIE):
1 = Indicates that a Catastrophic Thermal Sensor trip based on a
higher to lower temperature transition thru the trip point
0 = No trip for this event
8
RWC
0b
Was Hot Thermal Sensor Interrupt Event (WHTSIE):
1 = Indicates that a Hot Thermal Sensor trip based on a higher to
lower temperature transition thru the trip point
0 = No trip for this event
Reserved
7:5
4
RO
00b
RWC
0b
Catastrophic Thermal Sensor Interrupt Event (CTSIE):
1 = Indicates that a Catastrophic Thermal Sensor trip event occurred
based on a lower to higher temperature transition thru the trip
point.
0 = No trip for this event Software must write a 1 to clear this status
bit.
3
RWC
0b
Hot Thermal Sensor Interrupt Event (HTSIE):
1 = Indicates that a Hot Thermal Sensor trip event occurred based on
a lower to higher temperature transition thru the trip point.
0 = No trip for this event Software must write a 1 to clear this status
bit.
2:0
RO
Reserved
00b
Datasheet
155
INTEL [ INTEL ]
