DRAM Controller Registers (D0:F0)
5.2.41
EPDREFCONFIG—EP DRAM Refresh Configuration
B/D/F/Type:
Address Offset:
Default Value:
Access:
0/0/0/MCHBAR
A30–A33h
40000C30h
RO, RW
Size:
32 bits
This register provides settings to configure the EPD refresh controller.
Bit
31
Access &
Default
Description
RO
0b
Reserved
30:29
RW
10b
EPDunit refresh count addition for self refresh exit.
(EPDREF4SR): Configuration indicating the number of additional
refreshes that needs to be added to the refresh request count after
exiting self refresh.
Typical value is to add 2 refreshes.
00 = Add 0 Refreshes
01 = Add 1 Refreshes
10 = Add 2 Refreshes
11 = Add 3 Refreshes
28
RW
0b
Refresh Counter Enable (REFCNTEN): This bit is used to enable
the refresh counter to count during times that DRAM is not in self-
refresh, but refreshes are not enabled. Such a condition may occur
due to need to reprogram DIMMs following DRAM controller switch.
This bit has no effect when Refresh is enabled (i.e. there is no mode
where Refresh is enabled but the counter does not run). Thus, in
conjunction with bit 23 REFEN, the modes are:
REFEN:REFCNTEN
Description
0:0
0:1
Normal refresh disable
Refresh disabled, but counter is accumulating
refreshes.
1:X
Normal refresh enable
27
26
RW
0b
Refresh Enable (REFEN):
0 = Disabled
1 = Enabled
RW
0b
DDR Initialization Done (INITDONE): Indicates that DDR
initialization is complete.
0 = Not Done
1 = Done
148
Datasheet
INTEL [ INTEL ]
