DRAM Controller Registers (D0:F0)
Bit
Access &
Default
Description
23:20
19:17
RW
0h
one-hot active rank population (ep_scr_actrank): This field
indicates the active rank in a one hot manner
RW
000b
CKE pulse width requirement in low phase
(sd0_cr_cke_pw_lh_safe): This field indicates CKE pulse width
requirement in low phase.
16:15
14
RO
0h
Reserved
RW
0b
EPDunit MPR mode (EPDMPR): MPR Read Mode
1 = MPR mode
0 = Normal mode
13
12
RW
0b
EPDunit Power Down enable for ODT Rank (EPDOAPDEN):
Configuration to enable the ODT ranks to dynamically enter power
down.
1 = Enable active power down.
0 = Disable active power down.
RW
0b
EPDunit Power Down enable for Active Rank (EPDAAPDEN):
Configuration to enable the active rank to dynamically enter power
down.
1 = Enable active power down.
0 = Disable active power down.
Reserved
11:10
9:1
RO
0h
RW
00000000
0b
Self refresh exit count (sd0_cr_slfrfsh_exit_cnt): This field
indicates the Self refresh exit count. (Program to 255)
0
RW
0b
indicates only 1 rank enabled (sd0_cr_singledimmpop): This
field indicates that only 1 rank is enabled.
146
Datasheet
INTEL [ INTEL ]
