DRAM Controller Registers (D0:F0)
5.2.33
EPC0DRA01—ME Channel 0 DRAM Rank 0,1 Attribute
B/D/F/Type:
Address Offset:
Default Value:
Access:
0/0/0/MCHBAR
A08–A09h
0000h
RW
16 bits
Size:
The DRAM Rank Attribute Registers define the page sizes/number of banks to be used
when accessing different ranks. These registers should be left with their default value
(all zeros) for any rank that is unpopulated, as determined by the corresponding
CxDRB registers. Each byte of information in the CxDRA registers describes the page
size of a pair of ranks. Channel and rank map:
Ch0 Rank0, 1:
Ch0 Rank2, 3:
Ch1 Rank0, 1:
Ch1 Rank2, 3:
108h – 109h
10Ah – 10Bh
188h – 189h
18Ah – 18Bh
Bit
Access &
Default
Description
15:8
7:0
RW
00h
Channel 0 DRAM Rank-1 Attributes (C0DRA1): This field defines
DRAM pagesize/number-of-banks for rank1 for given channel.
RW
Channel 0 DRAM Rank-0 Attributes (C0DRA0): This field defines
00h
DRAM pagesize/number-of-banks for rank0 for given channel.
5.2.34
EPC0DRA23—ME Channel 0 DRAM Rank 2,3 Attribute
B/D/F/Type:
Address Offset:
Default Value:
Access:
0/0/0/MCHBAR
A0A–A0Bh
0000h
RW
16 bits
Size:
See C0DRA01 register.
Bit
15:8
7:0
Access &
Default
Description
RW
00h
Channel 0 DRAM Rank-3 Attributes (C0DRA3): This field defines
DRAM pagesize/number-of-banks for rank3 for given channel.
RW
Channel 0 DRAM Rank-2 Attributes (C0DRA2): This field defines
00h
DRAM pagesize/number-of-banks for rank2 for given channel.
142
Datasheet
INTEL [ INTEL ]
