DRAM Controller Registers (D0:F0)
5.2.10
C0CYCTRKWR—Channel 0 CYCTRK WR
B/D/F/Type:
Address Offset:
Default Value:
Access:
0/0/0/MCHBAR
256–257h
0000h
RW
16 bits
Size:
This register provides Channel 0 CYCTRK WR.
Bit
Access &
Default
Description
15:12
RW
0h
ACT To Write Delay (C0sd_cr_act_wr): This field indicates the
minimum allowed spacing (in DRAM clocks) between the ACT and
WRITE commands to the same rank-bank. This field corresponds to
tRCD_wr in the DDR Specification.
11:8
7:4
RW
0h
Same Rank Write To Write Delay (C0sd_cr_wrsr_wr): This field
indicates the minimum allowed spacing (in DRAM clocks) between two
WRITE commands to the same rank.
RW
0h
Different Rank Write to Write Delay (C0sd_cr_wrdr_wr): This
field indicates the minimum allowed spacing (in DRAM clocks)
between two WRITE commands to different ranks. This field
corresponds to tWR_WR in the DDR Specification.
3:0
RW
0h
READ To WRTE Delay (C0sd_cr_rd_wr): This field indicates the
minimum allowed spacing (in DRAM clocks) between the READ and
WRITE commands. This field corresponds to tRD_WR
.
Datasheet
123
INTEL [ INTEL ]
