DRAM Controller Registers (D0:F0)
5.2.6
C0DRA01—Channel 0 DRAM Rank 0,1 Attribute
B/D/F/Type:
Address Offset:
Default Value:
Access:
0/0/0/MCHBAR
208–209h
0000h
R/W
16 bits
Size:
The DRAM Rank Attribute Registers define the page sizes/number of banks to be used
when accessing different ranks. These registers should be left with their default value
(all zeros) for any rank that is unpopulated, as determined by the corresponding
CxDRB registers. Each byte of information in the CxDRA registers describes the page
size of a pair of ranks. Channel and rank map:
Ch 0, Rank 0, 1= 208h–209h
Ch 0, Rank 2, 3 = 20Ah–20Bh
Ch 1, Rank 0, 1= 608h–609h
Ch 1, Rank 2, 3= 60Ah–60Bh
DRA[7:0] = "00" means Cfg 0 , DRA[7:0] ="01" means Cfg 1 .... DRA[7:0] = "09" means Cfg 9
and so on.
Table 5-3. DRAM Rank Attribute Register Programming
Cfg
Tech
DDRx
Depth
Width
Row
Col
Bank
Row
Size
Page
Size
0
1
2
3
4
5
6
7
256Mb
256Mb
512Mb
512Mb
512Mb
512Mb
1 Gb
2
2
32M
16M
64M
32M
64M
32M
128M
64M
8
16
8
13
13
14
13
13
12
14
13
10
9
2
2
2
2
3
3
3
3
256 MB
128 MB
512 MB
256 MB
512 MB
256 MB
1 GB
8k
4k
8k
8k
8k
8k
8k
8k
2
10
10
10
10
10
10
2
16
8
3
3
16
8
2,3
2,3
1 Gb
16
512 MB
Bit
Access &
Default
Description
15:8
7:0
R/W
00h
Channel 0 DRAM Rank-1 Attributes (C0DRA1): This field defines
DRAM pagesize/number-of-banks for rank1 for given channel. See
Table 5-3 for programming.
R/W
00h
Channel 0 DRAM Rank-0 Attributes (C0DRA0): This field defines
DRAM page size/number-of-banks for rank0 for given channel. See
Table 5-3 for programming.
120
Datasheet
INTEL [ INTEL ]
