DRAM Controller Registers (D0:F0)
Bit
Access &
Default
Description
15
RW
0b
Read ODT Not Always Safe (sd0_cr_rdodtnas): Internal Read
ODT to CS is not always safe. Setting this bit selects the delay
(programmable) in the ODT Read Safe register field.
14
RW
0b
Write ODT Not Always Safe (sd0_cr_wrodtnas): Internal Write
ODT to CS is not always safe. Setting this bit selects the delay
(programmable) in the ODT Write Safe register field.
13:10
RW
0010b
Minimum Power-down exit to Non-Read command spacing
(sd0_cr_txp): This field indicates the minimum number of clocks to
wait following assertion of CKE before issuing a non-read command.
0000–0001 = Reserved
0010–1001 = 2–9clocks
1010–1111 = Reserved
9:1
0
RW
00000000
0b
Self refresh exit count (sd0_cr_slfrfsh_exit_cnt): This field
indicates the Self refresh exit count. (Program to 255). This field
corresponds to tXSNR/tXSRD in the DDR Specification.
RW
0b
Indicates only 1 DIMM populated (sd0_cr_singledimmpop): This
bit, when set, indicates that only 1 DIMM is populated.
5.2.14
C0REFRCTRL—Channel 0 DRAM Refresh Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
0/0/0/MCHBAR
269–26Eh
021830000C30h
RW, RO
Size:
48 bits
This register provides settings to configure the DRAM refresh controller.
Bit
Access &
Default
Description
47:42
41:37
RO
00h
Reserved
RW
10000b
Direct Rcomp Quiet Window (DIRQUIET): This field indicates the
amount of refresh_tick events to wait before the service of rcomp
request in non-default mode of independent rank refresh.
36:32
31:27
26
RW
11000b
Indirect Rcomp Quiet Window (INDIRQUIET): This field indicates
the amount of refresh_tick events to wait before the service of rcomp
request in non-default mode of independent rank refresh.
RW
00110b
Rcomp Wait (RCOMPWAIT): This field indicates the amount of
refresh_tick events to wait before the service of rcomp request in
non-default mode of independent rank refresh.
RW
0b
Reserved
126
Datasheet
INTEL [ INTEL ]
