DRAM Controller Registers (D0:F0)
5.2.4
C0DRB2—Channel 0 DRAM Rank Boundary Address 2
B/D/F/Type:
Address Offset:
Default Value:
Access:
0/0/0/MCHBAR
204–205h
0000h
RO, R/W
16 bits
Size:
See C0DRB0 register for programming information.
Bit
15:10
9:0
Access &
Default
Description
RO
000000b
Reserved
R/W
000h
Channel 0 DRAM Rank Boundary Address 2 (C0DRBA2): This
register defines the DRAM rank boundary for rank2 of Channel 0
(64 MB granularity)
= (R2 + R1 + R0)
R0 = Total Rank 0 memory size is 64 MB
R1 = Total Rank 1 memory size is 64 MB
R2 = Total Rank 2 memory size is 64 MB
R3 = Total Rank 3 memory size is 64 MB
5.2.5
C0DRB3—Channel 0 DRAM Rank Boundary Address 3
B/D/F/Type:
Address Offset:
Default Value:
Access:
0/0/0/MCHBAR
206–207h
0000h
R/W, RO
16 bits
Size:
See C0DRB0 register for programming information.
Bit
15:10
9:0
Access &
Default
Description
RO
000000b
Reserved
R/W
000h
Channel 0 DRAM Rank Boundary Address 3 (C0DRBA3): This
register defines the DRAM rank boundary for rank3 of Channel 0
(64 MB granularity)
= (R3 + R2 + R1 + R0)
R0 = Total Rank 0 memory size is 64 MB
R1 = Total Rank 1 memory size is 64 MB
R2 = Total Rank 2 memory size is 64 MB
R3 = Total Rank 3 memory size is 64 MB
Datasheet
119
INTEL [ INTEL ]
