DRAM Controller Registers (D0:F0)
Bit
Access &
Default
Description
25
RW
0b
Refresh Counter Enable (REFCNTEN): This bit is used to enable
the refresh counter to count during times that DRAM is not in self-
refresh, but refreshes are not enabled. Such a condition may occur
due to need to reprogram DIMMs following DRAM controller switch.
This bit has no effect when Refresh is enabled (i.e., there is no mode
where Refresh is enabled but the counter does not run). Thus, in
conjunction with bit 23 REFEN, the modes are:
REFEN:REFCNTEN
Description
0:0
0:1
Normal refresh disable
Refresh disabled, but counter is accumulating
refreshes.
1:X
Normal refresh enable
24
23
RW
0b
All Rank Refresh (ALLRKREF): This configuration bit enables (by
default) that all the ranks are refreshed in a staggered/atomic
fashion. If set, the ranks are refreshed in an independent fashion.
RW
0b
Refresh Enable (REFEN):
0 = Disabled
1 = Enabled
22
RW
0b
DDR Initialization Done (INITDONE): Indicates that DDR
initialization is complete.
0 = Not Done
1 = Done
21:20
19:18
RW
00b
Reserved
RW
00b
DRAM Refresh Panic Watermark (REFPANICWM): When the
refresh count exceeds this level, a refresh request is launched to the
scheduler and the dref_panic flag is set.
00 = 5
01 = 6
10 = 7
11 = 8
17:16
RW
00b
DRAM Refresh High Watermark (REFHIGHWM): When the
refresh count exceeds this level, a refresh request is launched to the
scheduler and the dref_high flag is set.
00 = 3
01 = 4
10 = 5
11 = 6
Datasheet
127
INTEL [ INTEL ]
