DRAM Controller Registers (D0:F0)
5.2.11
C0CYCTRKRD—Channel 0 CYCTRK READ
B/D/F/Type:
Address Offset:
Default Value:
Access:
0/0/0/MCHBAR
258–25Ah
000000h
RW, RO
24 bits
Size:
This register provides Channel 0 CYCTRK RD.
Bit
Access &
Default
Description
23:21
20:17
RO
000b
Reserved
RW
0h
Min ACT To READ Delay (C0sd_cr_act_rd): This field indicates the
minimum allowed spacing (in DRAM clocks) between the ACT and
READ commands to the same rank-bank. This field corresponds to
tRCD_rd in the DDR Specification.
16:12
11:8
RW
00000b
Same Rank Write To READ Delay (C0sd_cr_wrsr_rd): This field
indicates the minimum allowed spacing (in DRAM clocks) between the
WRITE and READ commands to the same rank. This field corresponds
to tWTR in the DDR Specification.
RW
0000b
Different Ranks Write To READ Delay (C0sd_cr_wrdr_rd): This
field indicates the minimum allowed spacing (in DRAM clocks) between
the WRITE and READ commands to different ranks. This field
corresponds to tWR_RD in the DDR Specification.
7:4
3:0
RW
0000b
Same Rank Read To Read Delay (C0sd_cr_rdsr_rd): This field
indicates the minimum allowed spacing (in DRAM clocks) between two
READ commands to the same rank.
RW
0000b
Different Ranks Read To Read Delay (C0sd_cr_rddr_rd): This
field indicates the minimum allowed spacing (in DRAM clocks) between
two READ commands to different ranks. This field corresponds to
tRD_RD
.
5.2.12
C0CYCTRKREFR—Channel 0 CYCTRK REFR
B/D/F/Type:
Address Offset:
Default Value:
Access:
0/0/0/MCHBAR
25B–25Ch
0000h
RO, RW
16 bits
Size:
This register provides Channel 0 CYCTRK Refresh.
Bit
Access &
Default
Description
15:13
12:9
RO
000b
Reserved
RW
0000b
Same Rank PALL to REF Delay (C0sd_cr_pchgall_rfsh): This
field indicates the minimum allowed spacing (in DRAM clocks)
between the PRE-ALL and REF commands to the same rank.
8:0
RW
000000000b
Same Rank REF to REF Delay (C0sd_cr_rfsh_rfsh): This field
indicates the minimum allowed spacing (in DRAM clocks) between
two REF commands to same ranks.
124
Datasheet
INTEL [ INTEL ]
