DRAM Controller Registers (D0:F0)
Bit
15:10
9:0
Access &
Default
Description
RO
000000b
Reserved
R/W
000h
Channel 0 Dram Rank Boundary Address 0 (C0DRBA0): This
register defines the DRAM rank boundary for rank0 of Channel 0
(64 MB granularity)
= R0
R0 = Total Rank 0 memory size is 64 MB
R1 = Total Rank 1 memory size is 64 MB
R2 = Total Rank 2 memory size is 64 MB
R3 = Total Rank 3 memory size is 64 MB
5.2.3
C0DRB1—Channel 0 DRAM Rank Boundary Address 1
B/D/F/Type:
Address Offset:
Default Value:
Access:
0/0/0/MCHBAR
202–203h
0000h
R/W, RO
16 bits
Size:
See C0DRB0 register for programming information.
Bit
15:10
9:0
Access &
Default
Description
RO
000000b
Reserved
R/W
000h
Channel 0 Dram Rank Boundary Address 1 (C0DRBA1): This
register defines the DRAM rank boundary for rank1 of Channel 0
(64 MB granularity)
= (R1 + R0)
R0 = Total Rank 0 memory size is 64 MB
R1 = Total Rank 1 memory size is 64 MB
R2 = Total Rank 2 memory size is 64 MB
R3 = Total Rank 3 memory size is 64 MB
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Datasheet
INTEL [ INTEL ]
