DRAM Controller Registers (D0:F0)
5.2.1
CHDECMISC—Channel Decode Miscellaneous
B/D/F/Type:
Address Offset:
Default Value:
Access:
0/0/0/MCHBAR
111h
00h
RW/L
8 bits
Size:
This register has Miscellaneous CHDEC/MAGEN configuration bits.
Bit
7
Access &
Default
Description
RW/L
0b
Reserved
6:5
RW/L
00b
Enhanced Mode Select (ENHMODESEL):
00 = Swap Enabled for Bank Selects and Rank Selects
01 = XOR Enabled for Bank Selects and Rank Selects
10 = Swap Enabled for Bank Selects only
11 = Reserved
4
3
RO
0b
Reserved
RW
0b
Ch1 Enhanced Mode (CH1_ENHMODE): This bit enables Enhanced
addressing mode of operation is enabled for Ch 1.
0 = Disable
1 = Enable
2
1
0
RW/L
0b
Ch0 Enhanced Mode (CH0_ENHMODE): This bit enables Enhanced
addressing mode of operation is enabled for Ch 0.
0 = Disable
1 = Enable
RW
0b
Flex Memory (FLXMEM): This bit disables the Flex mode memory
configuration.
0 = Enable
1 = Disable
RW
0b
ME Present (EPPRSNT): This bit indicates whether ME UMA is
present in the system or not.
0 = Not Present
1 = Present
116
Datasheet
INTEL [ INTEL ]
