DRAM Controller Registers (D0:F0)
Address
Offset
Symbol
C1DRA01
C1DRA23
Register Name
Default
Value
Access
RW,
608–609h
60A–60Bh
Channel 1 DRAM Rank 0,1
Attributes
0000h
0000h
Channel 1 DRAM Rank 2,3
Attributes
RW
650–651h
652–655h
656–657h
658–65Ah
660–663h
C1CYCTRKPCHG
C1CYCTRKACT
C1CYCTRKWR
C1CYCTRKRD
C1CKECTRL
Channel 1 CYCTRK PCHG
Channel 1 CYCTRK ACT
Channel 1 CYCTRK WR
Channel 1 CYCTRK READ
Channel 1 CKE Control
0000h
00000000h
0000h
RO, RW
RO, RW
RW,
000000h
00000800h
RO, RW
RW,
RW, RO
669–66Eh
C1REFRCTRL
Channel 1 DRAM Refresh
Control
021830000
C30h
RW, RO
69C–69Fh
A00– A01h
C1ODTCTRL
EPC0DRB0
Channel 1 ODT Control
00100000h
0000h
RO, RW
RW, RO
EP Channel 0 DRAM Rank
Boundary Address 0
A02– A03h
A04– A05h
A06– A07h
A08– A09h
A0A– A0Bh
A19– A1Ah
A1C– A1Fh
A20– A21h
A22– A23h
A24– A26h
A28– A33h
A2Eh
EPC0DRB1
EPC0DRB2
EPC0DRB3
EPC0DRA01
EPC0DRA23
EP Channel 0 DRAM Rank
Boundary Address 1
0000h
0000h
RO, RW
RO, RW
RW, RO
RW
EP Channel 0 DRAM Rank
Boundary Address 2
EP Channel 0 DRAM Rank
Boundary Address 3
0000h
EP Channel 0 DRAM Rank 0,1
Attribute
0000h
EP Channel 0 DRAM Rank 2,3
Attribute
0000h
RW
EPDCYCTRKWRT
PRE
EPD CYCTRK WRT PRE
EPD CYCTRK WRT ACT
EPD CYCTRK WRT WR
EPD CYCTRK WRT REF
EPD CYCTRK WRT READ
0000h
RW, RO
RO, RW
RW, RO
RO, RW
RW
EPDCYCTRKWRT
ACT
00000000h
0000h
EPDCYCTRKWRT
WR
EPDCYCTRKWRT
REF
0000h
EPDCYCTRKWRT
RD
000000h
EPDCKECONFIG
REG
EPD CKE related configuration
registers
00E000000
0h
RW
MEMEMSPACE
ME Memory Space
Configuration
00h
RW, RO
RO, RW
A30–A33h
EPDREFCONFIG
EP DRAM Refresh Configuration
40000C30h
114
Datasheet
INTEL [ INTEL ]
