INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT
Table 1. Lead Descriptions
(Continued)
Symbol
BYTE#
Type
INPUT
Name and Function
E
BYTE ENABLE:
BYTE# low places the device in x8 mode. All data is then input
or output on DQ
0
–DQ
7
, while DQ
8
–DQ
15
float. Address A
0
selects between the
high and low byte. BYTE# high places the device in x16 mode, and turns off the
A
0
input buffer. Address A
1
then becomes the lowest order address.
ERASE / PROGRAM / BLOCK LOCK ENABLE:
For erasing array blocks,
programming data, or configuring lock-bits.
With V
PEN
≤
V
PENLK
, memory contents cannot be altered.
V
PEN
INPUT
V
CC
V
CCQ
SUPPLY
DEVICE POWER SUPPLY:
With V
CC
≤
V
LKO
, all write attempts to the flash
memory are inhibited.
OUTPUT
OUTPUT BUFFER POWER SUPPLY:
This voltage controls the device’s output
BUFFER voltages. To obtain output voltages compatible with system data bus voltages,
SUPPLY connect V
CCQ
to the system supply voltage.
SUPPLY
GROUND:
Do not float any ground pins.
NO CONNECT:
Lead is not internally connected; it may be driven or floated.
GND
NC
8
ADVANCE INFORMATION
INTEL [ INTEL CORPORATION ]
