E
Symbol
A
0
Type
INPUT
A
1
–A
22
INPUT
DQ
0
–DQ
7
DQ
8
–DQ
15
INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT
Table 1. Lead Descriptions
Name and Function
BYTE-SELECT ADDRESS:
Selects between high and low byte when the device
is in x8 mode. This address is latched during a x8 program cycle. Not used in
x16 mode (i.e., the A
0
input buffer is turned off when BYTE# is high).
ADDRESS INPUTS:
Inputs for addresses during read and program operations.
Addresses are internally latched during a program cycle.
32-Mbit: A
0
–A
21
64-Mbit: A
0
–A
22
INPUT/
LOW-BYTE DATA BUS:
Inputs data during buffer writes and programming, and
OUTPUT inputs commands during Command User Interface (CUI) writes. Outputs array,
query, identifier, or status data in the appropriate read mode. Floated when the
chip is de-selected or the outputs are disabled. Outputs DQ
6
–DQ
0
are also
floated when the Write State Machine (WSM) is busy. Check SR.7 (Status
Register bit 7) to determine WSM status.
INPUT/
HIGH-BYTE DATA BUS:
Inputs data during x16 buffer writes and programming
OUTPUT operations. Outputs array, query, or identifier data in the appropriate read mode;
not used for Status Register reads. Floated when the chip is de-selected, the
outputs are disabled, or the WSM is busy.
INPUT
CHIP ENABLES:
Activates the device’s control logic, input buffers, decoders,
and sense amplifiers. When the device is de-selected (see Table 2,
Chip Enable
Truth Table
), power reduces to standby levels.
All timing specifications are the same for these three signals. Device selection
occurs with the first edge of CE
0
, CE
1
, or CE
2
that enables the device. Device
deselection occurs with the first edge of CE
0
, CE
1
, or CE
2
that disables the
device (see Table 2,
Chip Enable Truth Table
).
CE
0
,
CE
1
,
CE
2
RP#
INPUT
RESET/ POWER-DOWN:
Resets internal automation and puts the device in
power-down mode. RP#-high enables normal operation. Exit from reset sets the
device to read array mode. When driven low, RP# inhibits write operations which
provides data protection during power transitions.
RP# at V
HH
enables master lock-bit setting and block lock-bits configuration
when the master lock-bit is set. RP# = V
HH
overrides block lock-bits thereby
enabling block erase and programming operations to locked memory blocks. Do
not permanently connect RP# to V
HH
.
OE#
WE#
INPUT
INPUT
OUTPUT ENABLE:
Activates the device’s outputs through the data buffers
during a read cycle. OE# is active low.
WRITE ENABLE:
Controls writes to the Command User Interface, the Write
Buffer, and array blocks. WE# is active low. Addresses and data are latched on
the rising edge of the WE# pulse.
STS
STATUS:
Indicates the status of the internal state machine. When configured in
OPEN
DRAIN level mode (default mode), it acts as a RY/BY# pin. When configured in one of
OUTPUT its pulse modes, it can pulse to indicate program and/or erase completion. For
alternate configurations of the STATUS pin, see the Configurations command.
Tie STS to V
CCQ
with a pull-up resistor.
ADVANCE INFORMATION
7
INTEL [ INTEL CORPORATION ]
