INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT
E
are valid. Likewise, the device has a wake time
(tPHWL) from RP#-high until writes to the CUI are
recognized. With RP# at GND, the WSM is reset
and the status register is cleared.
available in 56-lead SSOP (Shrink Small Outline
Package) and µBGA* package (micro Ball Grid
Array). The 32-Mbit is available in 56-lead TSOP
(Thin Small Outline Package), 56-lead SSOP, and
56-bump µBGA packages. Figures 2, 3, and 4
show the pinouts.
The Intel StrataFlash memory devices are
available in several package types. The 64-Mbit is
DQ0 - DQ15
VCCQ
Output Buffer
Input Buffer
VCC
Query
I/O Logic
BYTE#
CE0
CE1
CE2
WE#
OE#
RP#
Identifier
Register
CE
Logic
Command
User
Interface
Status
Register
Multiplexer
Data
Comparator
Y-Decoder
X-Decoder
Y-Gating
STS
32-Mbit: A - A21
64-Mbit: A00 - A22
Input Buffer
Write State
Machine
VPEN
Program/Erase
Voltage Switch
32-Mbit: Thirty-two
64-Mbit: Sixty-four
128-Kbyte Blocks
Address
Latch
VCC
GND
Address
Counter
0606_01
Figure 1. Intel StrataFlash™ Memory Block Diagram
6
ADVANCE INFORMATION
INTEL [ INTEL ]
