E
INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT
CONTENTS
PAGE
PAGE
5.0 DESIGN CONSIDERATIONS ........................40
5.1 Three-Line Output Control..........................40
5.2 STS and Block Erase, Program, and Lock-
Bit Configuration Polling ............................40
5.3 Power Supply Decoupling ..........................40
5.4 V
CC
, V
PEN
, RP# Transitions........................40
5.5 Power-Up/Down Protection ........................41
5.6 Power Dissipation.......................................41
6.0 ELECTRICAL SPECIFICATIONS..................42
6.1 Absolute Maximum Ratings ........................42
6.2 Operating Conditions..................................42
6.3 Capacitance ...............................................42
6.4 DC Characteristics .....................................43
6.5 AC Characteristics— Read-Only
Operations.................................................45
6.6 AC Characteristics— Write Operations.......48
6.7 Block Erase, Program, and Lock-Bit
Configuration Performance........................51
7.0 ORDERING INFORMATION.........................52
8.0 ADDITIONAL INFORMATION ......................53
1.0 PRODUCT OVERVIEW ...................................5
2.0 PRINCIPLES OF OPERATION .....................11
2.1 Data Protection ..........................................12
3.0 BUS OPERATION .........................................12
3.1 Read ..........................................................13
3.2 Output Disable ...........................................13
3.3 Standby......................................................13
3.4 Reset/Power-Down ....................................13
3.5 Read Query................................................14
3.6 Read Identifier Codes.................................14
3.7 Write ..........................................................14
4.0 COMMAND DEFINITIONS ............................14
4.1 Read Array Command................................18
4.2 Read Query Mode Command.....................18
4.2.1 Query Structure Output .......................18
4.2.2 Query Structure Overview ...................20
4.2.3 Block Status Register ..........................21
4.2.4 CFI Query Identification String.............22
4.2.5 System Interface Information...............23
4.2.6 Device Geometry Definition .................24
4.2.7 Primary-Vendor Specific Extended
Query Table .......................................25
4.3 Read Identifier Codes Command ...............26
4.4 Read Status Register Command................27
4.5 Clear Status Register Command................27
4.6 Block Erase Command ..............................27
4.7 Block Erase Suspend Command................27
4.8 Write to Buffer Command...........................28
4.9 Byte/Word Program Commands.................28
4.10 Configuration Command...........................29
4.11 Set Block and Master Lock-Bit
Commands................................................29
4.12 Clear Block Lock-Bits Command..............30
ADVANCE INFORMATION
3
INTEL [ INTEL CORPORATION ]
