INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT
E
Table 16. Status Register Definitions
WSMS
bit 7
ESS
bit 6
ECLBS
bit 5
PSLBS
bit 4
VPENS
bit 3
R
DPS
bit 1
R
bit 2
bit 0
High Z
When
Busy?
Status Register Bits
SR.7 = WRITE STATE MACHINE STATUS
NOTES:
No
Yes
Yes
Check STS or SR.7 to determine block
erase, program, or lock-bit configuration
completion. SR.6–SR.0 are not driven while
SR.7 = “0.”
1
0
= Ready
= Busy
SR.6 = ERASE SUSPEND STATUS
1
0
= Block Erase Suspended
= Block Erase in Progress/Completed
If both SR.5 and SR.4 are “1”s after a block
erase or lock-bit configuration attempt, an
improper command sequence was entered.
SR.5 = ERASE AND CLEAR LOCK-BITS
STATUS
SR.3 does not provide a continuous
1
0
= Error in Block Erasure or Clear Lock-Bits
programming voltage level indication. The
= Successful Block Erase or Clear Lock-Bits WSM interrogates and indicates the
programming voltage level only after Block
Yes
Yes
SR.4 = PROGRAM AND SET LOCK-BIT STATUS
Erase, Program, Set Block/Master Lock-Bit,
or Clear Block Lock-Bits command
sequences.
1
= Error in Programming or Set Master/Block
Lock-Bit
0
= Successful Programming or Set
Master/Block Lock Bit
SR.1 does not provide a continuous
indication of master and block lock-bit
values. The WSM interrogates the master
lock-bit, block lock-bit, and RP# only after
Block Erase, Program, or Lock-Bit
configuration command sequences. It
informs the system, depending on the
attempted operation, if the block lock-bit is
set, master lock-bit is set, and/or RP# is not
SR.3 = PROGRAMMING VOLTAGE STATUS
1
= Low Programming Voltage Detected,
Operation Aborted
0
= Programming Voltage OK
Yes
Yes
SR.2 = RESERVED FOR FUTURE
ENHANCEMENTS
SR.1 = DEVICE PROTECT STATUS
V
HH. Read the block lock and master lock
1
= Master Lock-Bit, Block Lock-Bit and/or
RP# Lock Detected, Operation Abort
= Unlock
configuration codes using the Read
Identifier Codes command to determine
master and block lock-bit status.
0
Yes
SR.0 = RESERVED FOR FUTURE
ENHANCEMENTS
SR.2 and SR.0 are reserved for future use
and should be masked when polling the
status register.
32
ADVANCE INFORMATION
INTEL [ INTEL ]
