INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT
E
Bus
Start
Command
Comments
Operation
Data = 28H or 20H
Addr = Block Address
Write
Read
Erase Block
Device Supports
Queuing
XSR.7 = Valid
Addr = X
Check XSR.7
Yes
Standby
Write
1 = Erase Queue Avail.
0 = No Erase Queue Avail.
Set Time-Out
Data = 28H
Addr = Block Address
Erase Block
Issue Block Queue Erase
Command 28H, Block
Address
SR.7 = Valid; SR.6 - 0 = X
With the device enabled,
OE# low updates SR
Addr = X
Read
No
Read Extended Status
Register
Check XSR.7
Standby
1 = Erase Queue Avail.
0 = No Erase Queue Avail.
Is Queue
Available?
XSR.7=
Erase
Confirm
Data = D0H
Addr = X
No
Erase Block
Time-Out?
0=No
Write (Note 1)
Status register data
With the device enabled,
OE# low updates SR
Addr = X
1=Yes
Read
Another
Block
Erase?
Check SR.7
1 = WSM Ready
0 = WSM Busy
Standby
Yes
Yes
1. The Erase Confirm byte must follow Erase Setup when
the Erase Queue status (XSR.7) = 0.
Yes
Issue Erase Command 28H
Block Address
1=No
Full status check can be done after all erase and write
sequences complete. Write FFH after the last operation to
reset the device to read array mode.
Read Extended
Status Register
No
Issue Single Block Erase
Command 20H, Block
Address
Is Queue Full?
XSR.7=
0=Yes
Write Confirm D0H
Block Address
Write Confirm D0H
Block Address
Another
Block
Erase?
Issue Read
Status Command
No
Read
Status Register
No
Suspend
Erase Loop
0
Yes
SR.7 =
1
Suspend Erase
Full Status
Check if Desired
Erase Flash
Block(s) Complete
0606_09
Figure 9. Block Erase Flowchart
36
ADVANCE INFORMATION
INTEL [ INTEL ]
