IA186ER/IA188ER
Data Sheet
16-Bit/8-Bit Microcontrollers with RAM
February 25, 2013
Bit [7]—DA → Disable Address. When set to 1, the multiplexed address bus is disabled
and the address is not driven on the address bus when ucs_n is asserted, providing
reduced power consumption. When 0, the address is driven onto the address bus (ad15–
ad0) during the address phase of a bus cycle when ucs_n is asserted. This bit is set to 0 at
reset.
– If bhe_n/aden_n (IA186ER) is held at 0 during the rising edge of res_n, the address
bus is always driven, regardless of the setting.
Bit [6]—Reserved → Set to 0.
Bits [5–3]—Reserved → Set to 1.
Bit [2]—R2 Ready Mode → When set to 1, the external ready is ignored. When 0, it is
required. The value of the R1–R0 bits determines the number of wait states inserted.
Bits [1–0]—R1–R0 Wait-State Value → The value of these bits determines the number of
wait states inserted into an access to the lcs_n memory area. This number ranges from 0
to 3 (R1–R0 = 00b to 11b).
5.1.21 SPBAUD (088h)
Serial Port BAUD Rate Divisor Register. The value in this register determines the number of
internal processor cycles in one phase (half-period) of the 32 x serial clock. The contents of
these registers must be adjusted to reflect the new processor clock frequency if power-save mode
is in effect. The baud rate divisor may be calculated from:
BAUDDIV = (Processor Frequency/(32 x baud rate)) -1
(Equation 2)
By setting the BAUDDIV to 0000h, the maximum baud rate of 1/32 of the internal processor
frequency clock is set. Setting BAUDDIV to 129 (81h) provides a baud rate of 9600 at 40 MHz.
The baud rate tolerance is +4.6% to –1.9% with respect to the actual serial port baud rate, not the
target baud rate (see Table 37).
Table 37. Baud Rates
Divisor Based on CPU Clock Rate
Baud Rate
300
600
1200
2400
4800
9600
14400
20 MHz 25 MHz 33 MHz 40 MHz
4166
2083
1041
520
260
130
42
5208
2604
1302
651
325
162
53
6875
3437
1718
859
429
214
71
8333
4166
2083
1041
520
260
85
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