IA186ER/IA188ER
Data Sheet
16-Bit/8-Bit Microcontrollers with RAM
February 25, 2013
correspond to a19–a13 of the 20-bit memory address. The remaining bits a12–a0 of the
base address are always 0.
– The base address may be any integer multiple of the size of the memory clock
selected in the MPCS register. For example, if the midrange block is 32 Kbytes, the
block could be located at 20000h or 28000h but not at 24000h.
– If the lcs_n chip select is inactive, the base address of the midrange chip selects can
be set to 00000h, because the lcs_n chip select is defined to be 00000h but is unused.
Because the base address must be an integer multiple of the block size, a 512K
MMCS block size can only be used with the lcs_n chip select inactive and the base
address of the midrange chip selects set to 00000h.
Bits [8–3]—Reserved → Set to 1.
Bit [2]—R2 Ready mode → This bit determines the mcs_n chip select ready mode.
When set to 1, an external ready is ignored. When 0, it is necessary. In each case, the
number of wait states inserted in an access is determined by the value of the R1 and R0
bits.
Bits [1–0]—R1–R0 → Wait-State Value. The value of these bits determines the number
of wait states inserted in an access. Up to three wait states can be inserted (R1–R0 = 00b
to 11b).
5.1.18 PACS (0a4h)
PeripherAl Chip Select Register. These Peripheral Chip Selects are asserted over a 256-byte
range with the same timing as the ad address bus. There are six chip selects, pcs6_n–pcs5_n and
pcs3_n–pcs0_n, that are used in either the user-locatable memory or I/O blocks. The pcs4_n
chip select is not implemented in the IA186ER or IA188ER. Excluding the areas used by the
ucs_n, lcs_n, and mcs_n chip selects, the memory block can be located anywhere within the
1-Mbyte address space. These chip selects may also be configured to access the 64-Kbyte
I/O space.
Programming the Peripheral Chip Selects uses the Peripheral Chip Select (PACS) and the pcs_n
and mcs_n Auxiliary (MPCS) registers. The PACS register establishes the base address,
configures the ready mode, and determines the number of wait states for the pcs3_n–pcs0_n
outputs.
The MPCS register configures the pcs6_n–pcs5_n pins to be either chip selects or address pins
a1 and a2. When these pins are configured as chip selects, the MPCS register determines the
ready and wait states for these output pins and whether they are active during memory or I/O bus
cycles. These pins are activated as chip selects by writing to the two registers (PACS and
MPCS). They are not active on reset. To configure and activate them as address pins, it is
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