IA186ER/IA188ER
Data Sheet
16-Bit/8-Bit Microcontrollers with RAM
February 25, 2013
Bit [6]—PSE → PSRAM Mode Enable. When set to 1, PSRAM support for the lcs_n
chip select memory space is enabled. The EDRAM, MDRAM, and CDRAM RCU
registers must be configured for auto refresh before PSRAM support is enabled. Setting
the enable bit (EN) in the enable RCU register (EDRAM, offset e4h) configures the
mcs3_n/rfsh_n as rfsh_n.
Bits [5–3]—Reserved → Set to 1.
Bit [2]—R2 → Ready Mode. When set to 1, the external ready is ignored. When 0, it is
required. The value of R1–R0 bits determines the number of wait states inserted.
Bits [1–0]—R1–R0 → Wait-State Value. The value of these bits determines the number
of wait states inserted into an access to the lcs_n memory area. This number ranges from
0 to 3 (R1–R0 = 00b to 11b).
5.1.20 UMCS (0a0h)
The Upper Memory Chip Select Register configures the UMCS pin, used for the top of memory.
On reset, the first fetch takes place at memory location FFFF0h and thus this area of memory is
usually used for instruction memory. The ucs_n defaults to an active state at reset with a
memory range of 64 Kbytes (F0000h to FFFFFh), external ready required, and three wait states
automatically inserted. The upper end of the memory range always ends at FFFFFh. The lower
end of this upper memory range is programmable. The value of the UMCS register is F03Bh at
reset (see Table 36).
Table 36. Upper-Memory Chip Select Register
15 14 13 12 11 10
9
8
7
DA
6
0
5
4
3
2
1
0
1
LB2–LB0 Reserved
Reserved R2 R1–R0
Bit [15]—Reserved → Set to 1.
Bits [14–12]—LB2–LB0 Lower Boundary → These bits determine the bottom of the
memory accessed by the ucs_n chip select. The UMCS Block-Size Programming Values
shown below list the possible block-size configurations (a 512-Kbyte maximum).
UMCS Block-Size Programming Values
Memory
Starting
Block Size Address LB2–LB0 Comments
64K
F0000h
E0000h
C0000h
80000h
111b
110b
100b
000b
Default
128K
256K
512K
–
–
–
Bits [11–8]—Reserved.
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