IA186ER/IA188ER
Data Sheet
16-Bit/8-Bit Microcontrollers with RAM
February 25, 2013
Note: This bit should be reset by software.
Bit [0]—OER Overrun Error Detected → When new data overwrites valid data in the
receive register (because it has not been read) an overrun error is detected setting this bit.
Note: This bit should be reset by software.
5.1.25 SPCT (080h)
Serial Port ConTrol Register. This register controls both transmit and receive parts of the serial
port. The value of the SPCT register is 0000h at reset (see Table 42).
Table 42. Serial Port Control Register
15 14 13
DMA
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved TXIE RXIE LOOP BRK BRKVAL PMODE WLGN STP TMODE RSIE RMODE
Bits [15 - 13]— DMA Control Field → Enables DMA transfers to and from serial port as
follows:
DMA Bits Receive
Transmit
No DMA
DMA1
000
001
010
011
100
101
110
111
No DMA
DMA0
DMA1
RESERVED
DMA0
DMA1
DMA0
No DMA
No DMA
DMA0
No DMA
No DMA
DMA1
DMA transfers to the serial port act as destination-synchronized transfers. DMA request
occurs when THRE is set to 1. Interrupts are disabled regardless of the state of TXIE
when DMA transfers are enabled.
DMA transfers from the serial port act as source-synchronized transfers. DMA request
occurs when RDR is set to 1. Interrupts are disabled regardless of the state of RXIE when
DMA transfers are enabled.
Bit [12]—Reserved → Set to 0.
Bit [11]—TXIE Transmitter Ready Interrupt Enable → This bit enables the generation of
an interrupt request whenever the transmit holding register is empty (THRE Bit [1]). The
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