IA186ER/IA188ER
Data Sheet
16-Bit/8-Bit Microcontrollers with RAM
February 25, 2013
19200
31
0
NA
NA
NA
39
NA
0
NA
NA
53
NA
NA
0
64
1
NA
NA
0
625 Kbaud
781.25 Kbaud
1.041 Mbaud
1.25 Mbaud
NA
The value of the SPBAUD register at reset is undefined (see Table 38).
Table 38. Serial Port Baud Rate Divisor Registers
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
BAUDDIV
Bits [15–0]—BAUDDIV Baud Rate Divisor → Defines the divisor for the internal
processor clock.
5.1.22 SPRD (086h)
Serial Port Receive Data Register. Data received over the serial port are stored in this register
until read. The data are received initially by the receive shift register (no software access)
permitting data to be received while the previous data are being read.
The RDR bit (Receive Data Ready) in the serial port status register indicates the status of the
SPRD register. A 1 indicates there is valid data in the receive register. The value of the SPRD
register is undefined at reset (see Table 39).
Table 39. Serial Port Receive Data Register
15 14 13 12 11 10
Reserved
9
8
7
6
5
4
3
2
1
0
RDATA
Bits [15–8]—Reserved.
Bits [7–0]—RDATA → Holds valid data if the RDR bit of the status register is set.
5.1.23 SPTD (084h)
Serial Port Transmit Data Register. Data is written to this register by software, with the values to
be transmitted by the serial port. Double buffering of the transmitter allows for the transmission
of data from the transmit shift register (no software access) while the next data are written into
the transmit register.
The THRE bit in the Serial Port Status register indicates whether there is valid data in the
SPTDregister. The THRE bit must be a 1 before writing data to this register to prevent
overwriting valid data that is already in the SPTD register. The value of the SPTD register is
undefined at reset (see Table 40).
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