IA186ER/IA188ER
Data Sheet
16-Bit/8-Bit Microcontrollers with RAM
February 25, 2013
Bits [1–0]—R1–R0 → Wait-State Value (see pcs3_n–pcs0_n Wait-State Encoding
above).
The pcs6_n–pcs5_n and pcs3_n–pcs0_n pins are multiplexed with the PIO pins. For these to
function as chip selects, the PIO mode and direction settings for these pins must be set to 0
for normal operation.
5.1.19 LMCS (0a2h)
The Low-Memory Chip Select (LMCS) Register configures the LMCS provided to facilitate
access to the interrupt vector table located at 00000h or the bottom of memory. The lcs_n pin is
not enabled at reset.
The LCS_n pin is enabled by any write to the LMCS register. The value of the LMCS register is
undefined at reset except DA, which is set to 0 (see Table 35).
Table 35. Low-Memory Chip Select Register
15
14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Res
UB2–UB0 Reserved
DA PSE Reserved R2 R1–R0
Bit [15]—Reserved → Set to 0.
Bits [14–12]—UB2–UB0 → Upper Boundary. These bits define the upper boundary of
memory accessed by the lcs_n chip select. The list below presents the possible block-size
configurations (a 512-Kbyte maximum).
LMCS Block-Size Programming Values
Memory
Ending
Block Size Address UB2–UB0
64K
0FFFFh
1FFFFh
3FFFFh
7FFFFh
000b
001b
011b
111b
128K
256K
512K
Bits [11–8]—Reserved → Set to 1.
Bit [7]—DA → Disable Address. When set to 1, the multiplexed address bus is disabled,
providing reduced power consumption. When 0, the address is driven onto the address
bus ad15–ad0 during the address phase of a bus cycle. This bit is set to 0 at reset.
– If bhe_n/aden_n (IA186ER) is held at 0 during the rising edge of res_n, the address
bus is always driven, regardless of the setting of DA.
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