IA186ER/IA188ER
Data Sheet
16-Bit/8-Bit Microcontrollers with RAM
February 25, 2013
necessary to write to both the PACS and MPCS registers. Pins pcs6_n–pcs5_n can be
configured for 0 to 3 wait states and pcs3_n–pcs0_n can be programmed for 0 to 15 wait states.
The value of the PACS register is undefined at reset (see Table 34).
Table 34. Peripheral Chip Select Register
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
BA19–BA11
Reserved R3 R2 R1–R0
Bits [15–7]—BA19–BA11 → Base Address bits correspond to Bits [19–11] of the 20-bit
programmable base address of the peripheral chip select block and determine the base
address. Because I/O addresses are only 16 bits wide, if the pcs_n chip selects are
mapped to I/O space, Bits BA19-16 must be set to 0000b. The pcs address ranges are
shown below.
Address Ranges of pcs Chip Selects
Range
pcs_n Line
pcs0_n
pcs1_n
pcs2_n
pcs3_n
Reserved
pcs5_n
pcs6_n
Low
High
Base Address
Base Address + 256
Base Address + 512
Base Address + 768
NA
Base Address + 255
Base Address + 511
Base Address + 767
Base Address + 1023
NA
Base Address + 1280 Base Address + 1535
Base Address + 1536 Base Address + 1791
Bits [6–4]—Reserved → Set to 1.
Bit [3]—R3 → Wait State Value. See pcs3_n–pcs0_n Wait-State Encoding shown below.
pcs3_n–pcs0_n Wait-State Encoding
R3 R1 R0 Wait States
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
2
3
5
7
9
15
Bit [2]—R2 → Ready Mode. When set to 1, external ready is ignored. When 0, it is
required. In each case the number of wait states is determined according to the
pcs3_n–pcs0_n Wait-State Encoding shown above.
IA211110517-02
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