IA186ER/IA188ER
Data Sheet
16-Bit/8-Bit Microcontrollers with RAM
February 25, 2013
respective port does not generate interrupts when this bit is 0. Interrupts continue to be
generated as long as THRE and the TXIE are 1.
Bit [10]—RXIE Receive Data Ready Interrupt Enable → This bit enables the generation
of an interrupt request whenever the receive register contains valid data (RDR Bit [1]).
The respective port does not generate interrupts when this bit is 0. Interrupts continue to
be generated as long as RDR and the RXIE are 1.
Bit [9]—LOOP Loop Back → The serial port is placed into the loop-back mode when
this bit is set.
Bit [8]—BRK Send Break → When this bit is set to 1, the txd/pio27 pin is driven to the
value in BRKVAL, overriding any data that may be in the course of being shifted out of
the transmit shift register.
Bit [7]—BRKVAL Break Value → This is the value transmitted when BRK is asserted.
Bits [6–5]—PMODE Parity Mode →See table below. These bits define parity checking
and generation 00 at reset.
Parity
None
Odd
Pmode
0x
10
Even
11
Bit [4]—WLGN Word Length → The number of bits transmitted or received in a frame is
determined by the value of this bit. When this bit is 1, the number of data bits in a frame
is 8. When 0, it is 7. This bit is 0 at reset.
Bit [3]—STP Stop Bits → This bit specifies the number of stop bits used to indicate the
end of a frame. When this bit is 1, the number of stop bits is 2. When 0, it is 1. This bit
is 0 at reset.
Bit [2]—TMODE Transmit Mode → When this bit is 1, the transmit section of the serial
port is enabled. When 0, it is disabled.
Bit [1]—RSIE Receive Status Interrupt Enable → When an exception occurs during data
reception, an interrupt request is generated if enabled by this bit (RSIE = 1). Interrupt
requests are made for the error conditions listed in the serial port status register (BRK,
OER, PER, and FER). This bit is 0 at reset.
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