IA186ER/IA188ER
Data Sheet
16-Bit/8-Bit Microcontrollers with RAM
February 25, 2013
Table 40. Serial Port Transmit Data Register
15 14 13 12 11 10
Reserved
9
8
7
6
5
4
3
2
1
0
TDATA
Bits [15–8]—Reserved.
Bits [7–0]—TDATA → Holds the data to be transmitted.
5.1.24 SPSTS (082h)
Serial Port STatuS Register. This register stores information concerning the current status of the
port. The status bits are described below.
The value of the SPSTS register is undefined at reset (see Table 41).
Table 41. Serial Port Status Register
15 14 13 12 11 10
Reserved
9
8
7
6
5
4
3
2
1
0
TEMT THRE RDR BRKI FER PER OER
Bits [15–7]—Reserved → Set to 0.
Bit [6]—TEMT Transmitter Empty → When both the transmit shift register and the
transmit register are empty, this bit is set indicating to software that it is safe to disable
the transmitter. This bit is read-only.
Bit [5]—THRE Transmit Holding Register Empty → When this bit is 1, the
corresponding transmit holding register is ready to accept data. This is a read-only bit.
Bit [4]—RDR Receive Data Ready → When this bit is 1, the SPRD register contains
valid data. This is a read_only bit and can be reset only by reading the receive register.
Bit [3]—BRKI Break Interrupt → This bit indicates that a break has been received when
this bit is set to 1 and causes a serial port interrupt request, if RSIE is set.
Note: This bit should be reset by software.
Bit [2]—FER Framing Error Detected → When the receiver samples the rxd/pio28 line as
low when a stop bit is expected (line high), a framing error is generated setting this bit.
Note: This bit should be reset by software.
Bit [1]—PER Parity Error Detected → When a parity error is detected in either mode 1 or
3, this bit is set.
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