IA186ER/IA188ER
Data Sheet
16-Bit/8-Bit Microcontrollers with RAM
February 25, 2013
they are configured as peripheral chip select pins. When 0, they become address bits a2
and a1, respectively.
Bit [6]—MS Memory/I/O Space Selector → This bit determines whether the pcs_n pins
are active during either memory or I/O bus cycles. When set to 1, the outputs are active
for memory bus cycles. When 0, they are active for I/O bus cycles.
Bits [5–3]—Reserved → Set to 1.
Bit [2]—R2 Ready Mode → This bit influences only the pcs6_n–pcs5_n chip selects.
When set to 1, external ready is ignored. When 0, it is required.
Bits [1–0]—R1–R0 Wait-State Value → These bits influence only the pcs6_n–pcs5_n
chip selects. Their value determines the number of wait states inserted into an access.
Up to three wait states can be inserted (R1–R0 = 00b to 11b).
5.1.17 MMCS (0a6h)
Midrange Memory Chip Select (MMCS) Register. Four chip-select pins, mcs3_n–mcs0_n, are
provided for use within a user-locatable memory block. Excluding the areas associated with the
ucs_n and lcs_n chip selects (and if mapped to memory, the address range of the peripheral chip
selects, pcs6_n–pcs5_n and pcs3_n–pcs0_n), the memory block base address can be located
anywhere within the 1-Mbyte memory address space. If the pcs_n chip selects are mapped to
I/O space, the mcs_n address range can overlap the pcs_n address range.
Two registers program the Midrange Chip Selects. The MMCS register determines the base
address, the ready condition, and wait states of the memory block that are accessed through the
mcs_n pins. The pcs_n and mcs_n auxiliary (MPCS) register configures the block size. On
reset, the mcs3_n–mcs0_n pins are not active. Both the MMCS and MPCS registers must be
written to activate these chip selects.
Unlike the ucs_n and lcs_n chip selects, the mcs3_n–mcs0_n outputs assert with the multiplexed
ad address bus (ad15–ad0 for the IA186ER and ao15–ao8 and ad7–ad0 for the IA188ER), rather
than the earlier timing of the a19–a0 bus. If the a19–a0 bus is used for address selection, the
timing is delayed for a half cycle later than that for ucs_n and lcs_n. The value is undefined at
reset (see Table 33).
Table 33. Midrange Memory Chip Select Register
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
BA19–BA13
Reserved
R2 R1–R0
Bits [15–9]—BA19–BA13 Base Address → The value of the this pin determines the base
address of the memory block that is addressed by the mcs_n chip select pins. These bits
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