IA186ER/IA188ER
Data Sheet
16-Bit/8-Bit Microcontrollers with RAM
February 25, 2013
decremented after each word transfer by 2 or by 1 for byte transfers. They are undefined at reset
(see Table 29).
Table 29. DMA Source Address High Register
15 14 13 12 11 10
Reserved
9
8
7
6
5
4
3
2
1
0
DSA19–DSA16
Bits [15–4]—Reserved.
Bits [3–0]—DSA19–DSA16 → DMA Source Address High bits are driven onto a19–a16
during the read phase of a DMA transfer.
5.1.14 D1SRCL (0d0h) and D0SRCL (0c0h)
DMA SouRCe Address Low Register. The 16 bits of these registers are combined with the 4 bits
of the respective DMA Source Address High register to produce a 20-bit source address. They
are undefined at reset (see Table 30).
Table 30. DMA Source Address Low Register
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
DSA15–DSA0
Bits [15–0]—DSA15–DSA0 → DMA Source Address Low bits are driven onto a15–a0
during the read phase of a DMA transfer.
5.1.15 IMCS (0ach)
Internal memory chip select register. This register controls the generation of chip select for the
Internal RAM. This memory can be mapped to any 32K byte boundary. An enable bit is used to
activate the memory rather than any write to the register. A separate control bit allows reads
from this memory to appear on the external bus. The value of this register is undefined at reset
(see Table 31).
Table 31. Internal Memory Chip Select Register
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
BA19 – BA13 SR RE
Reserved
Bits [15 – 11] — Base Address → Upper five bits of 20-bit memory address to which
internal memory is mapped. Undefined at reset.
Bit [10] — SR (Show Read) → When high, drives data on the external AD bus during
read of internal memory. Zero at reset.
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