IA186ER/IA188ER
Data Sheet
16-Bit/8-Bit Microcontrollers with RAM
February 25, 2013
Bits [15–0]—TC15–TC0 → DMA Transfer Count contains the transfer count for the
respective DMA channel. Its value is decremented after each transfer.
5.1.11 D1DSTH (0d6h) and D0DSTH (0c6h)
The DMA DeSTination Address High Register. The 20-bit destination address consists of these
4 bits combined with the 16 bits of the respective Destination Address Low Register. A DMA
transfer requires that two complete 16-bit registers (high and low registers) be used for both the
source and destination addresses of each DMA channel involved. These four registers must be
initialized. Each address may be incremented or decremented independently of each other after
each transfer. The addresses are incremented or decremented by two for word transfers and
incremented or decremented by one for byte transfers. They are undefined at reset (see
Table 27).
Table 27. DMA Destination Address High Register
15 14 13 12 11 10
Reserved
9
8
7
6
5
4
3
2
1
0
DDA19–DDA16
Bits [15–4]—Reserved.
Bits [3–0]—DDA19–DDA16 → DMA Destination Address High bits are driven onto
a19–a16 during the write phase of a DMA transfer.
5.1.12 DIDSTL (0d4h) and D0DSTL (0c4h)
DMA DeSTination Address Low Register. The 16 bits of these registers are combined with the
4 bits of the respective DMA Destination Address High Register to produce a 20-bit destination
address. They are undefined at reset (see Table 28).
Table 28. DMA Destination Address Low Register
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
DDA15–DDA0
Bits [15–0]—DDA15–DDA0 → DMA Destination Address Low bits are driven onto
a15–a0 during the write phase of a DMA transfer.
5.1.13 D1SRCH (0d2h) and D0SRCH (0c2h)
DMA SouRCe Address High Register. The 20-bit source address consists of these 4 bits
combined with the 16 bits of the respective Source Address Low Register. A DMA transfer
requires that two complete 16-bit registers in the PCB (high and low registers) be used for both
the source and destination addresses of each DMA channel involved. Each channel requires that
all four address registers be initialized. Each address may be independently incremented or
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