IA186ER/IA188ER
Data Sheet
16-Bit/8-Bit Microcontrollers with RAM
February 25, 2013
Synchronization Bit Channel Selection
SYN1 SYN0
Sync Type
Unsynchronized
Source Synchronized
Destination Synchronized
Reserved
0
0
1
1
0
1
0
1
Bit [5]—P → Relative Priority. When set to 1, selects high priority for this channel
relative to the other channel during simultaneous transfers.
Bit [4]—TDRQ → Timer 2 Synchronization. When set to 1, enables DMA requests from
Timer 2. When 0, disables them.
Bit [3]—Reserved.
Bit [2]—CHG → Change Start Bit. This bit must be set to 1 to allow modification of the
ST bit during a write. During a write, when CHG is set to 0, ST is not changed when
writing the control word. The result of reading this bit is always 0.
Bit [1]—ST → Start/Stop DMA Channel. When set to 1, the DMA channel is started.
The CHG bit must be set to 1 for this bit to be modified during the register write. A
processor reset causes this bit to be set to 0.
Bit [0]—Bn/W → Byte/Word Select. When set to 1, word transfers are selected.
When 0, byte transfers are selected.
Note: Word transfers are not supported if the chip selects are programmed
for 8-bit transfers. The IA188ER does not support word transfers
5.1.10 D1TC (0d8h) and D0TC (0c8h)
DMA Transfer Count Registers. The DMA Transfer Count registers are maintained by each
DMA channel. They are decremented after each DMA cycle. The state of the TC bit in the
DMA control register has no influence on this activity. If unsynchronized transfers are
programmed or if the TC bit in the DMA control word is set, DMA activity ceases when the
transfer count register reaches 0. The D0TC and D1TC registers are undefined at reset (see
Table 26).
Table 26. DMA Transfer Count Registers
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
TC15–TC0
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