fido2100 3-Port Industrial Ethernet DLR Switch with IEEE1588
Data Sheet
April 10, 2013
9.2.7 Target Time2 Register
Mnemonic
type offset bits 15
R/W 0x1C
14
0
13
0
12
0
11
0
10
0
9
0
9
0
9
0
9
0
8
7
6
0
6
0
6
0
6
0
5
0
5
0
5
0
5
0
4
0
4
0
4
0
4
0
3
0
3
0
3
0
3
0
2
0
2
0
2
0
2
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
TgtTim2_Lo_Lo
Target2[15:0]
Power-up Defaults
0
0
8
0
7
Mnemonic
type offset bits 15
R/W 0x1E
14
0
13
0
12
0
11
0
10
0
TgtTim2_Lo_Hi
Target2[31:16]
Power-up Defaults
0
0
8
0
7
Mnemonic
type offset bits 15
R/W 0x20
14
0
13
0
12
0
11
0
10
0
TgtTim2_Hi_Lo
Target2[47:32]
Power-up Defaults
0
0
8
0
7
Mnemonic
type offset bits 15
R/W 0x22
14
0
13
0
12
0
11
0
10
0
TgtTim2_Hi_Hi
Target2[63:48]
Power-up Defaults
0
0
0
The Target Time2 register consists of four 16-bit registers. When the system time is equal
to the target time value, the ttp2 bit in the Time Sync Event register is set and an interrupt
is generated to the Host if the ttm2 bit in the Time Sync Control register is also set. Reads
and writes of four 16-bit registers can be performed in any order. In order to prevent
spurious interrupts during writes, the tte2 bit should be ‘0’ in the Time Sync Control
register when writing to any of the four 16-bit registers. As explained under the ppse bit
in Time Sync Control register, the Target Time2 register can also be used to generate a
pulse per second output on the pps_sig pin.
9.2.8 External Event 1 Snapshot Register
Mnemonic
type offset bits 15
0x24
Power-up Defaults
14
13
12
11
0
10
0
9
0
9
0
8
7
6
0
6
5
0
5
0
4
0
4
0
3
0
3
0
2
0
2
0
1
0
1
0
0
0
0
0
Evnt1_Lo_Lo
R
Evnt1Snap[15:0]
0
0
0
0
0
8
0
7
Mnemonic
type offset bits 15
0x26
Power-up Defaults
14
0
13
0
12
0
11
0
10
0
Evnt1_Lo_Hi
R
Evnt1Snap[31:16]
0
0
0
0
56
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