fido2100 3-Port Industrial Ethernet DLR Switch with IEEE1588
Data Sheet
April 10, 2013
The System Time register consists of four 16-bit registers. The system timer is a loadable
up-counter and reflects the local time in the module. The system timer is incremented
when the Accumulator register rolls over. When performing reads, SysTime_Lo_Lo
should be read first, which will cause the higher 48-bits of the internal system time
register to be latched. When other SysTime_XX_XX registers are read later, the latched
value will be returned. When performing writes, the lower three SysTime_XX_XX
should be written first, and when SysTime_Hi_Hi is written later, the internal system
time register will be updated with the full 64 bit value.
9.2.6 Target Time1 Register
Mnemonic
type offset bits 15
R/W 0x14
14
0
13
0
12
0
11
0
10
0
9
0
9
0
9
0
9
0
8
7
6
0
6
0
6
0
6
0
5
0
5
0
5
0
5
0
4
0
4
0
4
0
4
0
3
0
3
0
3
0
3
0
2
0
2
0
2
0
2
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
TgtTim1_Lo_Lo
Target1[15:0]
Power-up Defaults
0
0
8
0
7
Mnemonic
type offset bits 15
R/W 0x16
14
0
13
0
12
0
11
0
10
0
TgtTim1_Lo_Hi
Target1[31:16]
Power-up Defaults
0
0
8
0
7
Mnemonic
type offset bits 15
R/W 0x18
14
0
13
0
12
0
11
0
10
0
TgtTim1_Hi_Lo
Target1[47:32]
Power-up Defaults
0
0
8
0
7
Mnemonic
type offset bits 15
R/W 0x1A
14
0
13
0
12
0
11
0
10
0
TgtTim1_Hi_Hi
Target1[63:48]
Power-up Defaults
0
0
0
The Target Time1 register consists of four 16-bit registers. When the system time is equal
to the target time value, the ttp1 bit in the Time Sync Event register is set and an interrupt
is generated to the Host if the ttm1 bit in the Time Sync Control register is also set. Reads
and writes of four 16-bit registers can be performed in any order. In order to prevent
spurious interrupts during writes, the tte1 bit should be ‘0’ in the Time Sync Control
register when writing to any of the four 16-bit registers.
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