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FIDO2100 参数 Datasheet PDF下载

FIDO2100图片预览
型号: FIDO2100
PDF下载: 下载PDF文件 查看货源
内容描述: fido2100 3端口工业以太网交换机DLR与IEEE 1588 [fido2100 3-Port Industrial Ethernet DLR Switch with IEEE 1588]
分类和应用: 以太网工业以太网
文件页数/大小: 84 页 / 2688 K
品牌: INNOVASIC [ INNOVASIC, INC ]
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fido2100 3-Port Industrial Ethernet DLR Switch with IEEE1588  
Data Sheet  
April 10, 2013  
The External Event 2 Snapshot register consists of four 16-bit registers. A rising edge on  
the input signal event_2_sig , triggers a snapshot of the System Time into Evnt2_XX_XX  
registers and the evs2 bit in Time Sync Event register is set. Polling of the Time Sync  
Event register for evs2 can be used to determine when this register is ready for a read.  
Reads of the four 16-bit registers can be performed in any order. The evs2 bit in the  
Time Sync Event register must be reset by writing a ‘1’ to it in order to snapshot the  
system time at the next rising edge of event_2_sig .  
9.2.10 Transmit Snapshot Register  
Mnemonic  
type offset bits 15  
0x34  
Power-up Defaults  
14  
13  
12  
0
11  
0
10  
0
9
8
7
6
5
0
5
0
4
0
4
0
3
0
3
0
2
0
2
0
1
0
1
0
0
0
0
0
TxTS_Lo_Lo  
R
TransmitSnap[15:0]  
0
0
0
0
9
0
8
0
7
0
6
Mnemonic  
type offset bits 15  
0x36  
Power-up Defaults  
14  
0
13  
0
12  
0
11  
0
10  
0
TxTS_Lo_Hi  
R
TransmitSnap[31:16]  
0
0
0
0
0
Mnemonic  
type offset bits 15  
0x38  
Power-up Defaults  
14  
0
13  
0
12  
0
11  
0
10  
0
9
8
7
6
5
0
5
0
4
0
4
0
3
0
3
0
2
0
2
0
1
0
1
0
0
0
0
0
TxTS_Hi_Lo  
R
TransmitSnap[47:32]  
0
0
0
0
0
Mnemonic  
type offset bits 15  
0x3A  
Power-up Defaults  
14  
0
13  
0
12  
0
11  
0
10  
0
9
8
7
6
TxTS_Hi_Hi  
R
TransmitSnap[63:48]  
0
0
0
0
0
The Transmit Snapshot register consists of four 16-bit registers. A Sync frame in master  
mode or Delay_Req frame in slave mode triggers a snapshot of the System Time into  
Xmit_XX_XX registers and the txs bit in Time Sync Event register is set. Reads of the  
four 16-bit registers can be performed in any order. The txs bit in the Time Sync Event  
register must be reset by writing a ‘1’ to it in order to snapshot system time at the next  
Sync or Delay_Req frame.  
9.2.11 Receive Snapshot Register  
Mnemonic  
type offset bits 15  
0x3C  
Power-up Defaults  
14  
13  
0
12  
0
11  
0
10  
0
9
8
7
6
5
0
4
0
3
0
2
0
1
0
0
0
RxTS_Lo_Lo  
R
ReceiveSnap[15:0]  
0
0
0
0
0
0
58  
support@innovasic.com  
1-505-883-5263  
Document #: IA211111101-04  
UNCONTROLLED WHEN PRINTED OR COPIED  
1-888-824-4184  
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