fido2100 3-Port Industrial Ethernet DLR Switch with IEEE1588
Data Sheet
April 10, 2013
Mnemonic
type offset bits 15
0x3E
Power-up Defaults
14
0
13
0
12
0
11
0
10
0
9
8
7
6
5
0
5
0
5
0
4
0
4
0
4
0
3
0
3
0
3
0
2
0
2
0
2
0
1
0
1
0
1
0
0
0
0
0
0
0
RxTS_Lo_Hi
R
ReceiveSnap[31:16]
0
0
9
0
8
0
7
0
6
Mnemonic
type offset bits 15
0x40
Power-up Defaults
14
0
13
0
12
0
11
0
10
0
RxTS_Hi_Lo
R
ReceiveSnap[47:32]
0
0
9
0
8
0
7
0
6
Mnemonic
type offset bits 15
0x42
Power-up Defaults
14
0
13
0
12
0
11
0
10
0
RxTS_Hi_Hi
R
ReceiveSnap[63:48]
0
0
0
0
0
The Receive Snapshot register consists of four 16-bit registers. A Sync frame in slave
mode or Delay_Req frame in master mode triggers a snapshot of the System Time into
the Recv_XX_XX registers and the rxs bit in Time Sync Event register is set. Reads of
four 16-bit registers can be performed in any order. Up to 16 snapshots will be stored in
the FIFO if firmware is slow to process them. If the FIFO is full, subsequent
Sync/Delay_Req frames will not cause the snapshot/source ID/sequence ID to be stored.
The rxs bit in the Time Sync Event register must be reset by writing a ‘1’ to it after
reading a snapshot. If the bit doesn’t reset, it indicates that additional snapshots are
present. Firmware should repeatedly read and store all entries from the FIFO until this bit
is reset.
9.2.12 Receive Source ID Register
Mnemonic
type offset bits 15
0x44
Power-up Defaults
14
13
0
12
0
11
0
10
0
9
0
9
0
9
0
8
7
6
0
6
0
6
0
5
0
5
0
5
0
4
0
4
0
4
0
3
0
3
0
3
0
2
0
2
0
2
0
1
0
1
0
1
0
0
0
0
0
0
0
RxID_Lo_Lo
R
SourceID[15:0]
0
0
0
8
0
7
Mnemonic
type offset bits 15
0x46
Power-up Defaults
14
0
13
0
12
0
11
0
10
0
RxID_Lo_Hi
R
SourceID[31:16]
0
0
8
0
7
Mnemonic
type offset bits 15
0x48
Power-up Defaults
14
0
13
0
12
0
11
0
10
0
RxID_Hi_Lo
R
SourceID[47:32]
0
0
0
59
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