fido2100 3-Port Industrial Ethernet DLR Switch with IEEE1588
Data Sheet
April 10, 2013
9.2.4 Accumulator Register
Mnemonic
type offset bits 15
R/W 0x08
14
0
13
0
12
0
11
0
10
0
9
8
7
6
5
0
5
0
4
0
4
0
3
0
3
0
2
0
2
0
1
0
1
0
0
0
0
0
Accum_Lo
Accumulator[15:0]
Power-up Defaults
0
0
9
0
8
0
7
0
6
Mnemonic
type offset bits 15
R/W 0x0A
14
0
13
0
12
0
11
0
10
0
Accum_Hi
Accumulator[31:16]
Power-up Defaults
0
0
0
0
0
The Accumulator register consists of two 16-bit registers. The Accumulator register
serves as a precision frequency divider in the time synchronization logic. Firmware
calculates a frequency scaling value to be written to the Addend register. The data in the
Accumulator register is added to the value in the Addend register once every period of
the system clock. When the Accumulator rolls over, an overflow pulse is asserted which
increments the value in the system timer. This register is not read or written to in normal
operation. When performing reads, Accum_Lo should be read first, which will cause the
higher 16 bits of the internal accumulator register to be latched and when Accum_Hi is
read later, the latched value will be returned. When performing writes, Accum_Lo should
be written first and when Accum _Hi is written later, the internal accumulator register
will be updated with the full 32-bit value.
9.2.5 System Time Register
Mnemonic
type offset bits 15
R/W 0x0C
14
0
13
0
12
0
11
0
10
0
9
0
9
0
9
0
9
0
8
7
6
0
6
0
6
0
6
0
5
0
5
0
5
0
5
0
4
0
4
0
4
0
4
0
3
0
3
0
3
0
3
0
2
0
2
0
2
0
2
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
SysTime_Lo_Lo
Systime[15:0]
Power-up Defaults
0
0
8
0
7
Mnemonic
type offset bits 15
R/W 0x0E
14
0
13
0
12
0
11
0
10
0
SysTime_Lo_Hi
Systime[31:16]
Power-up Defaults
0
0
8
0
7
Mnemonic
type offset bits 15
R/W 0x10
14
0
13
0
12
0
11
0
10
0
SysTime_Hi_Lo
Systime[47:32]
Power-up Defaults
0
0
8
0
7
Mnemonic
type offset bits 15
R/W 0x12
14
0
13
0
12
0
11
0
10
0
SysTime_Hi_Hi
Systime[63:48]
Power-up Defaults
0
0
0
54
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