fido2100 3-Port Industrial Ethernet DLR Switch with IEEE1588
Data Sheet
April 10, 2013
txs bit is set. If this bit is set and the txm bit in TS_Control register is also set,
an interrupt will be delivered to the Host. This bit can be reset by writing a ‘1’
to it.
rxs
Receive Snapshot. A Sync frame in slave mode or a Delay_Req frame in
master mode will cause a snapshot of the System time to be saved in the
Receive Snapshot register, the source ID/sequence ID of incoming frame to be
saved in the Receive Source ID/Sequence ID registers and the rxs bit to be set.
Up to 16 snapshots will be stored in the FIFO if firmware is slow to process
them. If the FIFO is full, subsequent Sync/Delay_Req frames will not cause a
snapshot/source ID/sequence ID to be stored. If this bit is set and the rxm bit
in TS_Control register is also set, an interrupt will be delivered to the Host.
This bit can be reset by writing a ‘1’ to it. If the bit doesn’t reset, it indicates
additional snapshots are present. Firmware should repeatedly read and store all
entries from the FIFO until this bit is reset.
9.2.3 Addend Register
Mnemonic
type offset bits 15
14
0
13
0
12
0
11
0
10
0
9
0
9
0
8
7
6
0
6
0
5
0
5
0
4
0
4
0
3
0
3
0
2
0
2
0
1
0
1
0
0
0
0
0
Addend_Lo
R/W 0x04
Addend[15:0]
Power-up Defaults
0
0
8
0
7
Mnemonic
type offset bits 15
R/W 0x06
14
0
13
0
12
0
11
0
10
0
Addend_Hi
Addend[31:16]
Power-up Defaults
0
0
0
The Addend register consists of two 16-bit registers. The Addend register contains the
frequency scaling value used by a firmware algorithm to achieve time synchronization in
the module. The value in this register is added to the value in the Accumulator. When the
Accumulator rolls over, an overflow pulse is asserted and increments system time.
Because the Addend register is cleared at reset, it must be written with a non-zero value
to allow system time to increment. Reads of the two 16-bit registers can be performed in
any order. When performing writes, Addend_Lo should be written first. When
Addend_Hi is written later, an internal addend register will be updated with the full 32-
bit value.
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