fido2100 3-Port Industrial Ethernet DLR Switch with IEEE1588
Data Sheet
April 10, 2013
Mnemonic
type offset bits 15
0x28
Power-up Defaults
14
0
13
0
12
0
11
0
10
0
9
0
9
0
8
7
6
5
0
5
0
4
0
4
0
3
0
3
0
2
0
2
0
1
0
1
0
0
0
0
0
Evnt1_Hi_Lo
R
Evnt1Snap[47:32]
0
0
8
0
7
0
6
Mnemonic
type offset bits 15
0x2A
Power-up Defaults
14
0
13
0
12
0
11
0
10
0
Evnt1_Hi_Hi
R
Evnt1Snap[63:48]
0
0
0
0
The External Event 1 Snapshot register consists of four 16-bit registers. A rising edge on
the input signal event_1_sig , triggers a snapshot of the System Time into Evnt1_XX_XX
registers and the evs1 bit in Time Sync Event register is set. Polling of the Time Sync
Event register for evs1 can be used to determine when this register is ready for a read.
Reads of the four 16-bit registers can be performed in any order. The evs1 bit in the
Time Sync Event register must be reset by writing a ‘1’ to it in order to snapshot the
system time at the next rising edge of event_1_sig .
9.2.9 External Event 2 Snapshot Register
Mnemonic
type offset bits 15
0x2C
Power-up Defaults
14
13
12
11
0
10
0
9
0
9
0
9
0
9
0
8
7
6
0
6
5
0
5
0
5
0
5
0
4
0
4
0
4
0
4
0
3
0
3
0
3
0
3
0
2
0
2
0
2
0
2
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
Evnt2_Lo_Lo
R
Evnt2Snap[15:0]
0
0
0
0
0
8
0
7
Mnemonic
type offset bits 15
0x2E
Power-up Defaults
14
0
13
0
12
0
11
0
10
0
Evnt2_Lo_Hi
R
Evnt2Snap[31:16]
0
0
8
0
7
0
6
Mnemonic
type offset bits 15
0x30
Power-up Defaults
14
0
13
0
12
0
11
0
10
0
Evnt2_Hi_Lo
R
Evnt2Snap[47:32]
0
0
8
0
7
0
6
Mnemonic
type offset bits 15
0x32
Power-up Defaults
14
0
13
0
12
0
11
0
10
0
Evnt2_Hi_Hi
R
Evnt2Snap[63:48]
0
0
0
0
57
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