fido2100 3-Port Industrial Ethernet DLR Switch with IEEE1588
Data Sheet
April 10, 2013
Mnemonic
type offset bits 15
0x4A
Power-up Defaults
14
0
13
0
12
0
11
0
10
0
9
0
8
7
6
0
5
0
4
0
3
0
2
0
1
0
0
0
RxID_Hi_Hi
R
SourceID[63:48]
0
0
0
The Receive Source ID register consists of four 16-bit registers. The reception of a Sync
frame in slave mode or Delay_Req frame in master mode triggers the capture of the
source ID field in the received frame into the RxID_XX_XX registers. Reads of the four
16-bit registers can be performed in any order. See the Receive Snapshot register for
additional description.
9.2.13 Receive Sequence ID Register
Mnemonic
type offset bits 15
0x4C
Power-up Defaults
14
13
12
0
11
0
10
0
9
8
7
6
5
0
4
0
3
0
2
0
1
0
0
0
RxSeqID
R
SequenceID[15:0]
0
0
0
0
0
0
0
The reception of a Sync frame in slave mode or Delay_Req frame in master mode
triggers the capture of the sequence ID field in the received frame into the RxSeqID
register. See the Receive Snapshot register for additional description.
9.2.14 PTP Sub-domain Register
Mnemonic
type offset bits 15
R/W 0x4E
14
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
3
2
0
1
0
0
0
Subdomain
Subdomain[7:0]
Power-up Defaults
0
0
0
0
The PTP Sub-domain register is used to specify the sub-domain field of PTP event
frames. Only the PTP event frames matching the value in this register will be time
stamped. By default, this register will be 0, matching only the default sub-domain event
frames.
9.2.15 Switch Control Register
Mnemonic
type offset bits 15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rst
0
SW_Control
R/W 0x50
ulfe dms dbs dfc dbg p2ly p1ly p2lo p1lo p2s p1s p2h p1h p2r p1r
Power-up Defaults
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
rst
Chip Reset. When a ‘1’ is written to this bit, all logic is returned to the same
default state as when a power-on reset occurs. This bit is self-clearing.
60
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