fido2100 3-Port Industrial Ethernet DLR Switch with IEEE1588
Data Sheet
April 10, 2013
rxm
Receive Snapshot Interrupt Mask. The receive snapshot interrupt mask
controls whether the receive snapshot rxs bit in the TS_Event register, should
interrupt the Host processor. When this bit is set, the interrupt to the Host is
enabled. When cleared, the interrupt to the Host is disabled.
9.2.2 Time Sync Interrupt Event Register
Mnemonic
type offset bits 15
R/W 0x02
14
13
12
11
0
10
0
9
0
8
0
7
0
6
0
5
4
3
2
1
0
TS_Event
rxs txs evs2 evs1 ttp2 ttp1
Power-up Defaults
0
0
0
0
0
0
0
0
0
0
All interrupt requests from Time Sync Event register will be delivered to the host CPU
through the ts_event_irq_n signal.
ttp1-2
Target Time Interrupt Pending 1-2. The Target Time interrupt pending 1-2
indicates if the corresponding Target Time register matched the System Time,
as explained under tte1-2 in the Time Sync Control register. If corresponding
ttm1-2 bit in the Time Sync Control register is also set, an interrupt will be
delivered to the Host. ttp1-2 can be reset by writing a ‘1’ to it.
evs1
Event 1 Snapshot. A rising edge on the input pin event_1_sig causes a
snapshot of the System Time to be saved in the External Event 1 Snapshot
register, and the evs1 bit to be set. After an event_1_sig, polling of this
register should take place in order to determine that a snapshot has taken place
when evs1 is set. Now the External Event 1 Snapshot register can be read. A
subsequent rising edge will not cause the snapshot to be updated while the
evs1 bit is set. This bit can be reset by writing a ‘1’ to it.
evs2
Event 2 Snapshot. A rising edge on the input pin event_2_sig causes a
snapshot of the System Time to be saved in the External Event 2 Snapshot
register, and the evs2 bit to be set. After an event_2_sig, polling of this
register should take place in order to determine that a snapshot has taken place
when evs2 is set. Now the External Event 2 Snapshot register can be read. A
subsequent rising edge will not cause the snapshot to be updated while the
evs2 bit is set. This bit can be reset by writing a ‘1’ to it.
txs
Transmit Snapshot. A Sync frame in master mode or Delay_Req frame in
slave mode will cause a snapshot of the System time to be saved in the
Transmit Snapshot register and the txs bit to be set. Subsequent
Sync/Delay_Req frames will not cause the snapshot to be updated while the
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