fido2100 3-Port Industrial Ethernet DLR Switch with IEEE1588
Data Sheet
April 10, 2013
9.2 Detailed Register Explanations
9.2.1 Time Sync Control Register
Mnemonic
type offset bits 15
R/W 0x00
14
13
0
12
0
11
0
10
0
9
8
7
6
5
4
3
2
1
0
TS_Control
rxm txm mm ppse tte2 tte1 evm2 evm1 ttm2 ttm1
Power-up Defaults
0
0
0
0
0
0
0
0
0
0
0
0
ttm1-2
Target Time Interrupt Mask 1-2. The Target Time interrupt mask 1-2
controls whether the corresponding Target Time interrupt is passed to the Host
processor. When any of these bits are set, the corresponding interrupt to the
Host is enabled. When any of these bits are cleared, the corresponding Target
Time interrupt to the Host is disabled.
evm1
evm2
tte1-2
Event 1 Interrupt Mask. The interrupt for the Host is always disabled,
regardless of the state of this bit.
Event 2 Interrupt Mask. The interrupt for the Host is always disabled,
regardless of the state of this bit.
Target Time Interrupt Enable 1-2. The Target Time interrupt enable 1-2
controls whether the corresponding Target Time interrupt is enabled. When
any of these bits are set, the corresponding Target Time Register is compared
with System Time Register. When they match, the corresponding ttp1-2 bit in
TS_Event register is set and the corresponding tte1-2 bit is reset. If the
corresponding ttm1-2 bit is also set then an interrupt is delivered to the Host.
To prevent spurious interrupts firmware should write to Target Time Registers
1-2, only when corresponding tte1-2 is not set.
ppse
mm
Pulse Per Second Enable. When this bit is set, the state of ttp2 bit in the
TS_Event register is reflected on output pin pps_sig.
Master Mode. When this bit is set, the Time Sync logic implementing IEEE
1588 ordinary clock hardware assist on the local port connected to the host
CPU MII interface, will operate in master mode. When this bit is reset the
same logic will operate in slave mode.
txm
Transmit Snapshot Interrupt Mask. The transmit snapshot interrupt mask
controls whether the transmit snapshot txs bit in the TS_Event register, should
interrupt the Host processor. When this bit is set, the interrupt to the Host is
enabled. When cleared, the interrupt to the Host is disabled.
51
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