OPTIREG™ SBC TLE9274QXV33
Serial Peripheral Interface
Field
Bits
Type
Description
DEV_STAT 7:6
rc
Device status before Restart mode
00B , Cleared (register must be actively cleared)
01B , Restart after failures (WD fail, TSD2, VCC1_UV and
VCC1_OV); also wake from SBC Fail-Safe mode
10B , Wake from Sleep mode
11B , Not used
RO_CL_HIG
H
5
rc
rc
rh
Reset PIN clamped to HIGH level detected
0B
1B
, No Reset Clamped to HIGH detected
, Reset Clamped to HIGH detected
FSI_FAIL
WD_FAIL
4
FSI fail information
0B
1B
, No FSI fail
, Failure on FSI pattern recognized
3:2
Number of WD-fail event
00B , No WD-fail
01B , 1x WD-fail, causing SBC activates FOx in Config1
10B , 2x WD-fails, causing SBC activates FOx in Config3
11B , Reserved (never achieved)
SPI_FAIL
1
rc
rc
SPI fail information
0B
1B
, No SPI fail
, Invalid SPI command detected, SPI command is not
executed
FO_ON_STA 0
Fail outputs on status
TE
0B
1B
, FO outputs are not activated
, FO outputs are activated
Notes
1. The bits DEV_STAT show the status of the device before it went through Restart. Either the device came from
regular Sleep mode (‘10’) or a failure (‘01’ - SBC Restart or SBC Fail-Safe mode: WD fail, TSD2 fail, VCC1_UV fail
or VCC1_OV if bit VCC1_OV_ RST is set) occurred.
2. The WD_FAIL bits are configured as a counter and are the only status bits which are cleared automatically by
the SBC. They are cleared after a successful watchdog trigger. See also Chapter 12.1.
3. The SPI_FAIL bit is cleared only by SPI command.
BUS_STAT_1
Bus communication status (Address 100 0100B)
POR / Soft Reset Value: 0000 0000B;
Restart Value: 0xx0 0xxxB
7
6
5
4
3
2
1
0
reserved
LIN1_FAIL_1 LIN1_FAIL_0
rc rc
reserved
reserved
CAN_FAIL_1 CAN_FAIL_0
VCAN_UV
r
r
r
r
rc
rc
rc
Datasheet
111
Rev.2.0
2022-05-06
INFINEON [ Infineon ]
