OPTIREG™ SBC TLE9274QXV33
Serial Peripheral Interface
Field
TEST
Bits
Type
Description
7
r
Status of TEST pin
0B
1B
, LOW Level (= 0)
, HIGH Level (= 1), SBC Development mode is enabled, No
reset triggered due to wrong watchdog trigger
reserved
6
5
r
r
Reserved, always reads as 1
CFG2_
STATE
Status of CFG2 bit on HW_CTRL register
This bit shows the setting in bit CFG2.
0B
, LOW Level; Fail outputs (FOx) are active after 2nd watchdog
trigger fail Config 3
1B
, HIGH Level; Fail outputs (FOx) are active after 1st watchdog
trigger fail Config 1
Reserved
WK
4:1
0
r
r
Reserved, always reads as 0
Status of WK
0B
1B
, LOW Level (= 0)
, HIGH Level (= 1)
SMPS_STAT
SMPS state (Address 100 1100B)
POR / Soft Reset Value: 0000 0xxxB;
Restart Value: xxxx 0xxxB
7
6
5
4
3
2
1
0
BST_ACT
BST_SH
BST_OP
BST_GSH
reserved
BCK_SH
BCK_OP
BCK_OOR
r
rc
rc
rc
rc
r
rc
rc
rc
Field
Bits
Type
Description
BST_ACT
BST_SH
BST_OP
7
6
5
rc
rc
rc
Boost regulator active
0B
1B
, Boost not active
, Boost active
BSTD and SNSP short detection
0B
1B
, No short detected on BSTD and SNSP pins
, BSTD or SNSP pins short to GND
BSTD, SNSP SNSN open detection
0B
1B
, No open detection in BSTD, SNSP and SNSN pins
, Or operation between: BSTD loss of diode detected, SNSP
loss of resistor detected, SNSN loss of GND detected
BST_GSH
Reserved
4
3
rc
r
BSTG pin short detection
0B
1B
, BSTG no short detected
, BSTG short detected to GND or internal supply
Reserved, always reads as 0
Datasheet
115
Rev.2.0
2022-05-06
INFINEON [ Infineon ]
