OPTIREG™ SBC TLE9274QXV33
Serial Peripheral Interface
Field
Bits
Type
Description
LIN4_FAIL
6:5
rc
LIN failure status
00B , No error
01B , LIN TSD shutdown, also TSD1 signaled
10B , LIN_TXD_DOM: TXDLIN dominant time out
11B , LIN_BUS_DOM: BUS dominant time out
LIN3_FAIL
LIN2_FAIL
4:3
2:1
0
rc
rc
r
LIN failure status
00B , No error
01B , LIN TSD shutdown, also TSD1 signaled
10B , LIN_TXD_DOM: TXDLIN dominant time out
11B , LIN_BUS_DOM: BUS dominant time out
LIN failure status
00B , No error
01B , LIN TSD shutdown, also TSD1 signaled
10B , LIN_TXD_DOM: TXDLIN dominant time out
11B , LIN_BUS_DOM: BUS dominant time out
Reserved
Notes
Reserved, always reads as 0
1. LIN recovery conditions:
1.) TXD Time Out: TXD goes HIGH or transmitter is set to wake capable or switched off.
2.) Bus dominant time out: Bus will become recessive or transceiver is set to wake capable or switched off.
3.) Supply undervoltage: as soon as the threshold is crossed again, i.e. VLIN > VS_UV.
4.) In all cases (also for TSD shutdown): to enable the bus transmission again, TXD needs to be HIGH for a
certain time (transmitter enable time).
WK_STAT_1
Wake-up source and information status (Address 100 0110B)
POR / Soft Reset Value: 0000 0000B;
Restart Value: x0xx 000xB
7
6
5
4
3
2
1
0
PFM_PWM
reserved
CAN_WU
TIMER_WU
reserved
reserved
reserved
WK_WU
r
rc
r
rc
rc
r
r
r
rc
Field
Bits
Type
Description
PFM_PWM
7
rc
PFM_PWM automatic transition detected
0B
1B
, No automatic PFM_PWM transition detected
, Automatic PFM_PWM transition detected
Reserved
CAN_WU
6
5
r
Reserved, always reads as 0
rc
Wake up via CAN bus
0B
1B
, No Wake up
, Wake up
Datasheet
113
Rev.2.0
2022-05-06
INFINEON [ Infineon ]
